Short Note on Costs of Floating Point Operations on current x86-64 Architectures: Denormals, Overflow, Underflow, and Division by Zero
نویسندگان
چکیده
Simple floating point operations like addition or multiplication on normalized floating point values can nowadays be computed by current AMD and Intel processors in three to five cycles. This is different for denormalized numbers, which appear when an underflow occurs and the value can no longer be represented as a normalized floating-point value. Here the costs are about two magnitudes larger. Often this is not noticed as this gradual underflow is normally avoided, by configuring the floating point units to tread underflowed values as zero, as described in section 2. The object of this short report is to quantify the performance impact on floating point operations when denormalized/NaN values, overflows, or divisions by zero occur. Hereby the focus is only on
منابع مشابه
Complete Interval Arithmetic and Its Implementation on the Computer
Let IIR be the set of closed and bounded intervals of real numbers. Arithmetic in IIR can be defined via the power set IPIR (the set of all subsets) of real numbers. If in case of division zero is not contained in the divisor arithmetic in IIR is an algebraically closed subset of the arithmetic in IPIR. Arithmetic in IPIR allows division by an interval that contains zero also. This results in c...
متن کاملError bounds on complex floating-point multiplication
Given floating-point arithmetic with t-digit base-β significands in which all arithmetic operations are performed as if calculated to infinite precision and rounded to a nearest representable value, we prove that the product of complex values z0 and z1 can be computed with maximum absolute error |z0| |z1| 12β √ 5. In particular, this provides relative error bounds of 2−24 √ 5 and 2−53 √ 5 for I...
متن کاملRepresentable Correcting Terms for Possibly Underflowing Floating Point Operations
Studying floating point arithmetic, authors have shown that the implemented operations (addition, subtraction, multiplication, division and square root) can compute a result and an exact correcting term using the same format as the inputs. Following a path initiated in 1965, many authors supposed that neither underflow nor overflow occurred in the process. Overflow is not critical as this kind ...
متن کاملAn Efficient Implementation of Floating Point Multiplier using Verilog
To represent very large or small values, large range is required as the integer representation is no longer appropriate. These values can be represented using the IEEE754 standard based floating point representation. Floating point multiplication is a most widely used operation in DSP/Math processors, robots, air traffic controller, digital computers. Because of its vast areas of application, t...
متن کاملFormal Verification of the VAMP Floating Point Unit
We report on the formal verification of the floating point unit used in the VAMP processor. The FPU is fully IEEE compliant, and supports denormals and exceptions in hardware. The supported operations are addition, subtraction, multiplication, division, comparison, and conversions. The hardware is verified on the gate level against a formal description of the IEEE standard by means of the theor...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید
ثبت ناماگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید
ورودعنوان ژورنال:
- CoRR
دوره abs/1506.03997 شماره
صفحات -
تاریخ انتشار 2015